As lithography allows for further scaling down of lateral dimensions in complementary metal oxide semiconductor (CMOS) devices, raised source and drain regions are being more commonly utilized to provide for a high performance transistor having ultra-shallow junctions. Raised source/drain regions, however, present a unique set of problems. For example, a physical facet is formed at the interfaces between the source/drain regions and the isolation field oxide of the transistor structure, and at the interfaces between the raised source/drain regions and the sidewall spacer adjacent to the gate conductor. Unfortunately, silicide contact can create a "spike" in these facets, and the spike may penetrate into the underlying substrate and through the shallow junction. Such a defect can lead to unwanted and detrimental device leakage.
The construction of transistors with raised source and drain regions demands highly controlled diffusion of dopants for creating the shallow junctions of the transistor. Current technology employs an ion implantation prior to deposition of the raised source and drain regions in order to form the electrical connection to the channel region of the device. However, the elevated temperatures inherent to the process of depositing the raised source and drain regions may cause the implanted dopant profile to further diffuse past the point of optimal device performance.
Further, the formation of silicided junctions can lead to problems when integrated with raised source and drain regions. When the gate conductor is not fully isolated from the raised source and drain regions, the silicided process can cause undesirable electrical contact between the gate and source and drain regions.
U.S. Pat. No. 4,998,150, issued Mar. 5, 1991, and U.S. Pat. No. 5,079,180, issued Jan. 7, 1992, both to Rodder and Chapman, disclose a raised "moat" region formed by epitaxial deposition. A thin sidewall insulator is used to allow lateral tailoring for the overlap capacitance while maintaining shallow transistor junctions. A second insulating spacer is used to separate the field insulating region and the raised source and drain regions. As a result, the tendency for silicide spike formation into the substrate is suppressed. Disadvantageously, the process disclosed requires scrupulous surface preparation and high temperature processing of epitaxial deposition. Further, a sidewall spacer is used to lengthen the distance between the raised source/drain regions and the top of the isolating gate. Deposition or growth of an epitaxial layer results in the formation of the raised source and drain regions. Rodder and Chapman acknowledges the drawbacks of high temperature processing, but unfortunately includes the associated anneal that causes unwanted diffusion of dopants within the substrate. Additionally, Rodder and Chapman limit the sidewall spacer thickness to 100-300 nm.
U.S. Pat. No. 5,118,639, issued Jun. 2, 1992, to Roth and Kirsch discloses forming elevated source and drain regions by depositing silicon onto prepared nucleation sites. These patterned sites allow the propagation of the selective deposition process. The end result of depositing such an electrically conductive material is a contact to the surface substrate with the gate electrode being isolated with insulating spacers and cap material. Roth and Kirsch assume the use of a high temperature selective polysilicon deposition, and suggest that the preparation of the nucleation site interface is marginal.
U.S. Pat. No. 4,072,545, issued Feb. 7, 1978, to De La Moneda discloses a decoupled source/drain fabrication from that of the contact. De La Moneda uses ion implantation for the contact and epitaxial deposition for the junctions. However, this patent requires the removal of gate oxide by wet etch, followed by the deposition of epitaxial silicon over the seed regions.
U.S. Pat. No. 4,948,745, issued Aug. 14, 1990, to Pfiester and Sivan discloses a process that uses the insulating cap over the gate electrode to pattern the gate. The cap is then removed to allow the second deposition of polysilicon. The second deposition of polysilicon extends laterally up onto the field oxide region. Pfiester and Sivan use sidewall spacers to isolate the elevated source/drain electrodes and the gate electrode. Again, such a structure is limited by the complexity of the growth of selective silicon.
Thus, there remains a need in semiconductor device technology for a reliable and manufacturable raised source/drain field effect structure.